It is generally desirable to make memory cells as small as possible so that more memory cells can be integrated into each chip. Higher capacitance storage capacitors also provide better definition when reading the memory cell, lower soft error rate, and enable lower voltage operation. Therefore, if memory cells can be made smaller and with higher capacitance, semiconductor memory devices can become more highly integrated.
Capacitors having three-dimensional structures have been proposed in an attempt to increase cell capacitance. These types of capacitors usually have a lower electrodes in the shape of a fin, a box, or a cylinder. However, the manufacturing processes for forming capacitors with three-dimensional electrode structures are complicated and defects may be easily generated during the manufacturing processes. Accordingly, research into the use of high dielectric materials for increasing the capacitance of capacitors is actively being conducted to avoid the need for forming capacitor electrodes having three-dimensional structure. However, when polysilicon doped with impurities is used as the lower electrode of a capacitor, the high dielectric layer may become susceptible to reaction with the polysilicon and this reaction may cause the formation of a parasitic dielectric layer having a relatively low dielectric constant at an interface between the lower electrode and the high dielectric layer. Accordingly, new electrodes which are less susceptible to reaction with high dielectric layers are required.
FIGS. 1 through 3 are sectional views illustrating a conventional method for manufacturing a capacitor of a semiconductor device. FIG. 1 shows the step of forming an interlayer dielectric layer pattern 20, a contact plug 30, a diffusion barrier layer 40 and a lower conductive layer 50. First, the interlayer dielectric layer pattern 20 having a contact hole therein for exposing a predetermined region of a semiconductor substrate 10, is formed on the semiconductor substrate 10. Then, a polysilicon layer is formed on the interlayer dielectric layer pattern 20 to fill the contact hole. The polysilicon layer is etched-back to expose the interlayer dielectric layer pattern 20, thereby forming the contact plug 30 filling the contact hole. Next, a diffusion barrier layer 40 and a lower conductive layer 50 are sequentially formed on the resultant structure. At this time, the diffusion barrier layer 40 is formed of titanium nitride, and the lower conductive layer 50 is formed of platinum (Pt) to inhibit the likelihood of reaction with a subsequently formed dielectric layer 60 (see FIG. 3). In particular, the diffusion barrier layer 40 is formed in order to prevent reaction between the contact plug 30 and the lower conductive layer 50 during the performance of a subsequent heat treatment process for forming the dielectric layer 60.
FIG. 2 shows the step of forming a diffusion barrier pattern 40a and a lower conductive layer pattern 50a. In detail, the lower conductive layer 50 and the diffusion barrier layer 40 are patterned to expose the interlayer dielectric layer pattern 20, and accordingly the diffusion barrier pattern 40a and the lower conductive layer pattern 50a which are sequentially stacked on the contact plug layer 30, are formed. This sequence of steps completes the lower electrode of the capacitor which consists of the contact plug layer 30, the diffusion barrier pattern 40a and the lower conductive layer pattern 50a.
FIG. 3 shows the step of completing the capacitor by forming a dielectric layer 60 and an upper conductive layer 70. In detail, the dielectric layer 60 (which may be formed of Pb(Zr, Ti)O.sub.3) and the upper conductive layer 70 are sequentially formed over the completed lower electrode, to complete the capacitor. At this time, the dielectric layer 60 is formed in an oxygen atmosphere in order to prevent oxygen deficiency in the dielectric layer 60. If there is no diffusion barrier pattern 40a, during the heat treatment process for forming the dielectric layer 60 the contact plug 30 and the lower conductive layer pattern 50a may react with each other to form a platinum silicide layer. The dielectric layer 60 and the silicon in the platinum silicide layer may then react with each other to form a parasitic dielectric layer (having a low dielectric constant) between the dielectric layer 60 and the platinum silicide layer. Accordingly, the total capacitance may be reduced. Therefore, the diffusion barrier pattern 40a is typically necessary for inhibiting any interface reaction between the contact plug 30 and the lower conductive layer pattern 50a. However, during formation of the dielectric layer 60, the sidewalls of the diffusion barrier pattern 40a are exposed to an atmosphere of oxygen and may become oxidized. Accordingly, the resistance of the diffusion barrier pattern 40a may be substantially increased.
According to the conventional method for manufacturing a semiconductor device, the diffusion barrier pattern 40a prevents reaction between the contact plug 30 and the lower conductive layer pattern 50a. However, oxidation which may occur during the process of forming the dielectric layer 60 typically increases the electrical resistance of the diffusion barrier pattern 40a. Accordingly, the total resistance of the lower electrode of the capacitor may be greatly increased and therefore the possibility of high speed operation of devices containing the above described storage capacitors may be limited. Also, when the diffusion barrier pattern 40a is oxidized, a dielectric material having a low dielectric constant may be formed in series with the dielectric layer 60 to reduce the total capacitance.